1. Field of the Invention
The present invention relates to a memory circuit, and more particularly to improvements in a dynamic memory circuit containing a cache memory.
2. Description of the Related Art
FIG. 1 shows the main portion of a conventional dynamic memory circuit with a built-in cache memory.
Each memory cell MC in a memory cell array is connected to a word line WL and a pair of bit lines BL and /BL. Each bit line pair BL, /BL is connected to a sense amplifier SA.
A cache memory 11 is composed of two inverter circuits I, I'. Here, the cache memory 11 holds data statically. The cache memory may be composed of two MOS transistors cross-coupled, in which case, the cache memory retains data dynamically.
Each first transfer gate 12 is composed of two n-channel MOS transistors N1, N1'. Each second transfer gate 13 is made up of two n-channel MOS transistors N2, N2'.
One end of each cache memory 11 is connected to the corresponding sense amplifier SA (bit line BL) via the corresponding first transfer gate 12, and also to one of the corresponding DQ-line pair (data-line pair) via the corresponding second transfer gate 13. The other end of each cache memory 11 is connected to the corresponding sense amplifier SA (bit line /BL) via the corresponding first transfer gate 12 and also to the other of the corresponding DQ-line pair via the corresponding second transfer gate 13.
The first transfer gate 12 is controlled by the output signal LWD of a first transfer gate control circuit 14. The first transfer gate control circuit 14 receives a write signal LW and outputs an output signal LWD.
The second transfer gates 13 are controlled by the output signal CSL of a column decoder 15.
In the dynamic memory device with a built-in cache memory thus constructed, data is written from the memory cell MC into the cache memory 11 by causing the first transfer gate control circuit 14 to enable the first transfer gate 12, thereby allowing the data read from the memory cell MC to be transferred to the cache memory 11 via the sense amplifier SA.
Thereafter, when the column decoder 15 enables the specific second transfer gate 13, the data stored in the cache memory 11 connected to the second transfer gate 13 is transferred to the corresponding DQ-line pair and outputted to the outside world via a buffer circuit 15A.
Data writing from the DQ-line pair into the cache memory 11 is effected by causing the column decoder 15 to enable the specific second transfer gate 13 and transferring the externally inputted data to the cache memory 11 via a buffer circuit 15B and the second transfer gate 13.
Thereafter, when the column decoder 15 enables the specific second transfer gate 13, the data stored in the cache memory 11 is transferred to the corresponding DQ-line pair and outputted to the outside world via the buffer circuit 15A.
With the recent trend toward increasingly faster memory devices, there is accordingly a demand in the field of dynamic memory circuits and those with a built-in cache memory toward higher-speed operation. To achieve higher-speed operation, they are designed to be synchronous memory circuits using external clock signals.
There are two cases where data is written into the cache memory in the dynamic memory circuit containing a cache memory: one case where the data read from the memory cell is written into and the other where the externally inputted data is written into.
In these cases where data is written into the cache memory, when the data to be written into the cache memory is the reverse of the data already written in the cache memory, the data already written in the cache memory must be reversed. The disadvantage of these cases is, therefore, that it takes a longer time to write data into the cache memory.
This disadvantage can be overcome by decreasing the driving power of the cache memory and increasing the driving power of the buffer that drives the sense amplifier and DQ-line pair and further increasing the driving power of the first and second transfer gates.
In this case, however, because the driving power of the sense amplifier becomes large, the operation margin in transferring data from the cache memory to the memory cell decreases and the driving power of the buffer for driving the DQ-line pair increases, resulting in a drop in the operation margin in transferring data from the cache memory to the DQ-line pair.